1. Field of the Invention
The present invention relates to a semiconductor device having a multilayer wiring structure and a method of fabricating the same.
2. Description of the Related Art
Semiconductor devices have been making progress in high integration year by year, and a reduction in the rules of circuit design has been introduced as the requirement for miniaturization. The reduction in the circuit design rules is directly related to a reduction in a circuit area. For example, in an integrated circuit having a multilayer wiring structure, a distance between adjacently formed via holes is reduced such that a distance between each via hole and metal wiring formed in an upper layer is also reduced at the same time.
Such a reduction in the distance between each via hole and the metal wiring further reduces a positioning margin in a lithography process, which renders the processing technique difficult. In addition, since a distance between adjacent wiring patterns is reduced, it becomes difficult to obtain a desired insulating property. When a sufficient distance of insulation is not obtained, there arises a problem of failure due to short circuit such as dielectric breakdown or direct short circuit or a problem of parasitic capacitance, resulting in a difficulty in achieving a stable device operation.
FIGS. 10A to 11B illustrate an example of the foregoing circumstances. FIG. 10A shows an example of multilayer wiring structure having no occurrence of patterning misalignment, whereas FIG. 10B shows an example of multilayer wiring structure in which misalignment has resulted from the patterning. As shown in these figures, an Al—Cu layer 2 serving as a lower wiring layer is formed on a silicon substrate 1. A titanium nitride (TiN) layer 3 serving as a barrier metal is formed on the Al—Cu layer 2. An interlayer wiring layer 4 is formed on the TiN layer 3. The interlayer wiring layer 4 has via holes each formed so as to extend vertically through a predetermined part of a dual tetraethyl orthosilane (d-TEOS) film 5. Contact plugs 6a and 6b made from tungsten (W) or the like are formed in the via holes respectively.
Barrier metal layers 7a and 7b each serving as an upper wiring layer, Al—Cu layers 8a and 8b and barrier metal layers 9a and 9b are patterned on the top of the interlayer wiring layer 4 so as to correspond to the locations of the contact plugs 6a and 6b. A distance d0 between electrodes in the upper wiring layer is, for example, 80 nm. In the case of FIG. 10B, there is an amount of misalignment A in the patterning of the upper wiring layer.
FIGS. 11A and 11B are sectional views corresponding to parts of the fabrication process respectively. As shown in FIG. 11A, the Al—Cu layer 2 and TiN film 3 of the lower wiring layer are formed, and the d-TEOS film 5 with a film thickness of 500 nm is formed on the TIN film 3. Tungsten as a material for the contact plugs 6a and 6b is buried in the via holes respectively.
In the state as shown in FIG. 11A, the TiN film 7, the Al—Cu film 8 of the upper wiring layer material and the TiN film 9 are formed on the d-TEOS film 5 serving as an interlayer insulating film, and resists 10a and 10b corresponding to a wiring circuit are patterned as shown in FIG. 11B. Misalignment occurs during a lithography process and an amount of misalignment A is, for example, 50 nm.
The TiN film 9, Al—Cu film 8 and TiN film 7 are etched by a reactive ion etching (RIE) process using a gas plasma such that the structure as shown in FIG. 10B is obtained. In this case, the TiN films 9a and 9b, Al—Cu films 8a and 8b, and TiN films 7a and 7b are electrically connected to the tungsten plugs 6a and 6b while misalignment has occurred by the misalignment amount A.
When the misalignment amount A is, for example, 30 nm as the result of occurrence of the foregoing misalignment, an insulation distance d1 between the upper wiring layer of the TiN film 9a, Al—Cu film 8a and TiN film 7a and the adjacent tungsten 6b becomes 50 nm. As a result, since a sufficient insulation distance can be ensured, no problem arises in the operation of the device. However, the insulation distance d1 becomes 30 nm when the misalignment amount A is increased to 50 nm. Consequently, there is a possibility of occurrence of a short circuit or an increase in the parasitic capacitance.
As one of conventional countermeasures, the specification of positioning in the lithography process has been reconsidered and/or the diameters of the via holes have been reduced. However, the reduction in the circuit design rules makes it difficult to obtain an insulation distance and at the same time, it is quite difficult to carry out further reconsideration of the positioning specification in view of the device performance. Further, variations in the diameter of the via hole also make it difficult to obtain a stable distance between insulators. Still further, at the same time, even when the diameter of the via hole is reduced, such reduction directly results in reduction in a junction area. As a result, a desired operation of the device cannot be achieved. Thus, the foregoing problem needs to be overcome for future fabrication of semiconductor circuits.
Accordingly, securement of the insulation distance and prevention of failure due to short circuit or parasitic capacitance are particularly important in the fabrication of multilayer wiring circuits in order that a stable device operation may be obtained against miniaturization of the device. JP-A-2000-208615 and JP-A-2002-176098 disclose the foregoing countermeasures.
JP-A-2000-208615 discloses an interlayer connection structure connecting upper and lower wiring layers of a semiconductor substrate. In this case, even upon occurrence of misalignment during the lithography process, a sufficient distance of electrical insulation can be ensured between contact portions adjacent to each other, whereby a sufficient contact area can be secured.
Further, JP-A-2002-176098 discloses a semiconductor device employing a structure that a lower side contact plug is previously recessed in the formation of a multilayer wiring circuit of a borderless structure so that a contact pattern at an upper wiring layer is prevented from reaching a contact plug due to misalignment, thereby preventing short circuit.
In each of the foregoing references, however, a width of a gap differs according to an amount of misalignment at the occasion of an etching process for recessing the contact plug, resulting in a problem of burying performance in the case where an interlayer insulating film is buried in an upper layer.